1. Field of the Invention
The present invention relates to input/output circuits which are utilized in fields requiring high speed interfaces between LSI's. In particular, input/output circuits of the invention are used for ATM branch exchanges and various kinds of computers.
2. Description of the Related Art
In the fields of large-scale computers or telecommunication systems or the like, it is desirous to achieve high speed, high integration, and lower power consumption for LSI's forming the systems. At present, no process exists for satisfying all requirements of the high speed, high integration, and lower power consumption. Therefore in these fields, a process is selected from plurality of process corresponding to the desired function (the high speed, high integration, or lower power consumption).
A CMOS process designates a graded characteristic in view of lower power consumption and high integration in LSI. In a CMOS process, CMOS logic circuits in an IC operate at high speed. This comes from recent developments of refining techniques. However, a lower speed of signal transmission between LSI's is provided in usual CMOS interfaces because MOSFET has a smaller current driving ability compared to bipolar (here particularly, "ECL" [emitter coupled logic]) and CMOS interface is a transmission system without impedance matching. The operating speed of the system is limited in forming a large scale system since the operating speed of the interface reaches the limit. It is one method that input and output are developed in a parallel manner in order to increase the interface speed. However, in this case, wirings on a mounting board and so forth increase corresponding to such parallel development of the input and output, and consequently the, mount area on the board is larger.
An advantage of ECL processes includes realizing a high speed transmission since the driving ability of elements is higher in the ECL process, and an input/output interfaces having impedance matching in receiving ends are used in the ECL interface system. However, the ECL process provides smaller integration and, in general, higher power consumption compared to CMOS.
Both advantages of the ECL process and CMOS process are realized in one process using a BICMOS process, in which the input/output is formed of ECL, and a logic circuit using CMOS is provided. The BICMOS process achieves high speed, high integration, and lower power consumption. However, the BICMOS processes having more complicated production process requires higher costs than in the CMOS or bipolar process. In addition, a characteristic exceeding that of the single process can hardly be obtained with respect to high speeds high integration, and lower power consumption.
We have proposed a high speed input/output circuit using CMOS and capable of exhibiting lower power consumption and high integration characteristics together with considerations of impedance matching, which is described in Japanese Patent Application HEI-2-325204 in 1990. FIG. 7 is a circuit diagram of the input/output circuit, where MOSFET circuits having double complimentary polarity used. Throughout this specification, MN represents NMOS FET, and MP represents PMOS FET.
In FIG. 7, numeral 101 depicts an output buffer circuit, 102 an input buffer circuit, 103 a transmission line connecting across the output buffer circuit 101 and the input buffer circuit 102.
In the output buffer circuit 101, I.sub.i1 depicts a current source for supplying current corresponding to a logic value H, and I.sub.i2 a current source for supplying current corresponding to a logic value L. Either of the current sources I.sub.i1 or I.sub.i2 is connected to a terminal 110 by turning a switch SW. The terminal 110 is connected to the transmission line 103.
In the input buffer circuit 102, 111 depicts an input terminal, which is connected to the transmission line 103. A source terminal of MN.sub.111 and a source terminal of MP.sub.111 are connected to the input terminal 111. A gate terminal of MN.sub.111 is connected to cathode-side of a voltage source V.sub.110 and the anode-side of a voltage source V.sub.111. The anode-side of the voltage source V.sub.110 is connected to a positive power supply V.sub.DD (terminal 10), a drain terminal of MN.sub.111 is connected to the positive power supply V.sub.DD (terminal 10), a gate terminal of MP.sub.111 is connected to cathode-side of the voltage source V.sub.111, and a drain terminal of MP.sub.111 is connected to a terminal 114, which is an output terminal of the input buffer circuit 102. The output terminal 114 is connected, for example, to the logic circuit through a current mirror circuit, which is omitted in the drawing.
Assuming that a signal input into the input buffer circuit 102 from the output buffer circuit 101 is of current form, and the current source I.sub.i1 is connected to the terminal 110 by the switch SW, where a current I.sub.H of the current source I.sub.i1 is input into the input buffer circuit 102 through the transmission line. A part of the current I.sub.H is absorbed in MN.sub.111 at the input buffer circuit 102. A current I.sub.B1 -I.sub.H being a difference between the bias current I.sub.B1 and the current I.sub.H of current source I.sub.i1 flows into MP.sub.111. The bias current I.sub.B1 is decided by MP.sub.111, MN.sub.111 and V.sub.111. Thus, a part of the signal I.sub.H is transmitted to the terminal 114. When the current source I.sub.i2 is connected to the terminal 110 by the switch SW, a reverse operation thereto is provided.
An input impedance of this circuit is equal to a paralleled impedance of MN.sub.111 and MP.sub.111, which is approximately shown by the following equation. EQU Zin=1/(gm,MN.sub.111 +gm,MP.sub.111)
where gm,MN.sub.111 represents transconductance of MN.sub.111, and gm,MP.sub.111 represents transconductance of MP.sub.111.
MN.sub.111 and MP.sub.111 are complementarily operated each other in the input buffer circuit 102 since gm is directly proportional to a square root of the operating current in the MOSFET. Thus, the current source dependency of the input impedance is smaller.
However in the input buffer circuit 102, some of the input current flows into the positive power supply V.sub.DD (terminal 10) through MN.sub.111 so that the input buffer circuit has a current gain of about 1/2 from the input terminal 111 to the output terminal 114, that is, a drawback of the input buffer circuit 102 includes a current gain of about 1/2 compared to the conventional example, in spite of easily obtaining impedance matching.